First impression on unpacking the Q702 test unit was the solid feel and clean, minimalist styling.
IBM aims new chip at smaller network gear
- — 25 March, 2002 08:45
IBM on Monday is set to unveil a processor for low-end and midrange networking equipment that will lead to faster access routers, firewalls and other gear, according to the company.
The PowerNP NP2G processor is IBM's latest salvo in a battle of programmable network processors, which are designed to make it easy for network equipment makers to quickly roll out faster and smarter systems. The new processor runs the same software architecture as the more powerful NP4SG3 and is pin-compatible with that chip, so it will be relatively easy for system manufacturers to start using the faster processor if customers start demanding more speed.
Programmable chips are gradually replacing ASICs (application specific integrated circuits) in network equipment because they let the makers of routers, switches and other systems change the capabilities of their products after they are in the field. They also let manufacturers build more powerful new models on largely the same platform used for existing products.
"It does end up being easier to design a system around these components than it used to be," said Linley Gwennap, principal analyst at The Linley Group, in Mountain View, California.
White Plains, New York-based IBM said its new chip outperforms Intel Corp.'s current IXP1200 processor on measures such as the number of instructions it can perform per second. The new chip offers sufficient "headroom" for a network device to not only perform basic networking functions but also run several added features such as security, QoS (quality of service) and load balancing, all without slowing down the packets going across the network, said Steve Longoria, director of IBM network processors. Competing processors from Intel, Motorola Inc. and other competitors are limited in how many special functions they can run if they are to keep packets running at top speed, he said.
In addition, it will be easier for system vendors to offer new capabilities on devices made with the NP2G, Longoria said. The chip has 12 packet processing engines that share a single 32K-byte, on-chip central memory repository. Because IBM uses a "run to completion" architecture instead of a "pipeline" model, a new application just has to be installed in one piece and all the engines can use it from the central repository. A pipeline model requires system vendors to distribute parts of the new application across the separate engines and then "rebalance" them, he said.
The shared memory also means each processing engine is less likely to run out of memory when its requirements spike, Longoria added.
Each of the 12 engines also has five hardware coprocessors that can handle extra work, so the engine itself can concentrate on basic networking functions such as protocol processing and queue management.
The NP2G is designed to support throughput of about 2G bps (bits per second). IBM expects most system vendors to connect two OC-12 (622M bps), two Gigabit Ethernet or 20 100M-bps Ethernet interfaces to each chip and deploy multiple chips across a large device. It may be used in desktop switches in enterprises, chassis-based edge routers and 3G (third-generation) wireless base stations, Longoria said. The new chip is shipping now in sample quantities and will be available in production volume in June. Systems built with the chip are likely to ship by the end of the year, Longoria said.
IBM is jumping in to meet growing demand for OC-12 products, a market it hasn't been able to exploit well with its more expensive NP4SG3 chip, which has a capacity of about 4G bps and was designed for OC-48 (2.5G bps) ports, Gwennap said. In part, the company is responding to a shift in the telecommunication industry as investment in high-speed backbones has slowed and service providers have focused on lower-speed connections closer to the edge, he said.
"As the market has gotten bigger and there's been a lot of opportunity in the low end, IBM wants to get a piece of the market," Gwennap said.
The NP2G has a big speed advantage against Intel's IXP1200, but IBM may find the new chip competing against the Intel IXP2400, a new, more powerful chip that is scheduled to begin shipping by the end of this year, Gwennap said. The IXP2400 is designed to support OC-48 interfaces. At a price projected by Intel at US$230, it won't be much more expensive than the new IBM chip, which IBM said will cost $195 in quantities of 10,000 units. In addition, Intel is preparing a new chip to replace the IXP1200.
"I'm not sure IBM's really going to sustain a performance advantage" over a long period, Gwennap said.
However, the "run to completion" architecture IBM uses in its network processors does offer an easier way for developers to add new capabilities to a chip, he added. In addition to IBM, Motorola and other network processor makers build their chips with this architecture. Intel says "run to completion" can be used on its chips, but it's not clear how much that would cost in terms of performance, Gwennap said.
Because Intel's chips lack the coprocessors and other performance-enhancing features of IBM's chips, it would take two Intel IXP2400 chips -- one for incoming traffic and one for outgoing -- to carry out the processes that a single IBM NP2G can perform, according to Longoria.