Sun's Niagara to use four on-chip memory controllers

Sun's Niagara chip will use four memory controllers to keep its eight cores filled with data and will consume 70 watts of power.

Sun Microsystems's upcoming Niagara processor will use four on-board memory controllers to keep the multicore, multithreaded processor running at maximum efficiency, according to the company's head processor designer.

Sun had spent much of 2005 promoting its new x86 servers, but the company was pressing forward with aggressive multicore, multithreaded Sparc processors code-named Niagara and Rock, vice-president and chief architect at Sun, Marc Tremblay, told the Fall Processor Forum.

The company plans to unveil servers based on Niagara starting early next year.

The first iteration of the Niagara family will be able to process 32 separate tasks at the same time, with eight processing cores capable of handling four software threads each.

An integrated memory controller was crucial to that design, Tremblay said. Putting the memory controller - which routes data between the processing cores and the memory -- on the processor allows the memory controller to run at the same frequency as the processor. This gets data into the chip as fast as it can be processed, improving chip efficiency.

In fact, four double data rate 2 (DDR2) memory controllers would be employed to keep Niagara's eight cores filled with data, Tremblay said.

"In Niagara, with a minimum of 32 outstanding transactions, you better have a pretty high memory bandwidth," he said.

Keeping those cores constantly filled with data also allowed Sun to use much smaller amounts of cache memory on Niagara as compared to the high-end processors Itanium 2 and Power 5 processors manufactured by Intel and IBM, respectively, Tremblay said.

Intel plans to use 24MB of cache on its forthcoming Montecito Itanium 2 processor, and IBM is using 36MB of cache on the Power 5 chip.

Cache memory stores data on the processor, instead of outside the chip in main memory. Chips without a fast connection to memory suffer when they have to leave the chip to find a piece of data.

Niagara would feature just 3MB of cache memory, Tremblay said, which allowed Sun to keep the eight-core Niagara processor small enough to maximise yields.

It also means that Niagara will be running flat out most of the time. One benefit of cache memory is that it consumes less power than other components on the processor. But with Niagara, Sun would eschew many of the dynamic power management techniques in development across the processor industry, Tremblay said.

This is possible because Niagara would only consume a maximum of 70 watts of power, Tremblay said. By contrast, Montecito would consume 100 watts of power under maximum operating conditions, which was less than the previous Itanium 2 processor.

Sun figures that Niagara might as well run as close to that 70 watt threshold as possible to ensure maximum performance, Tremblay said. Other chipmakers used clock speed and voltage throttling techniques to shut off areas of a processor that were not in use, but when Niagara noticed a drop-off in demand from one area of the chip it would switch the next thread in the queue to that area.

Niagara would be at or near the top in most measurements of performance per watt, which was quickly becoming one of the most important performance metrics when evaluating a new server, Tremblay said.

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Tom Krazit

IDG News Service
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