As scientists delve deeper into nanoelectronics, a problem they're confronting is power leakage. To help clear this hurdle, the European Commission is funding a consortium of research groups to the tune of Euro 4.5 million (AU$7.25 million).
The R&D (research and development) project aims to enhance the design of next-generation system-on-chip semiconductors by addressing the issue of power leakage in CMOS (complementary metal oxide semiconductor) technology of 65 nanometers and below, STMicroelectronics NV, a lead partner in the consortium, said Tuesday in a statement.
The project, called CLEAN (Controlling Leakage power in NanoCMOS SoCs), will receive a grant under the "Nanoelectronics" initiative as part of the Commission's 6th Framework Program, which supports a number of advanced R&D projects over a five-year period.
Power leakage has emerged as an obstacle in the development of nanoelectronic circuits with sub-65 nanometer technologies, according to STMicroelectronics. Design methods and processes for new semiconductor problems will need to evolve hand-in-hand to overcome this obstacle, it said.
CLEAN's main objectives will be the development of new generation power leakage models, design methods and techniques for leakage control and prototype EDA (Electronic Design Automation) tools. These tools will automatically perform portions of the design work, which today is unfeasible for highly complex systems.
The consortium consists of 14 partners, including Infineon Technologies, ChipVision Design Systems, the Technical University of Denmark and the Budapest University of Technology and Economics.