TI plans more efficient chips for mobile devices

Texas Instruments plans to build a more efficient family of 45-nanometer geometry processors by 2008 for multimedia handsets and smartphones.

To handle high computing loads in multimedia handsets and smartphones, Texas Instruments plans to build a faster, more efficient family of processors by 2008, the company announced Monday.

Texas Instruments (TI), of Dallas, said it will move to a 45-nanometer semiconductor manufacturing process for its system-on-chip (SoC) processors, increasing performance by 30 percent while reducing power consumption by 40 percent.

By balancing the demands of performance, power consumption and transistor density, the chip will be best suited for mobile phone processors and digital signal processors (DSPs), said Hans Stork, senior vice president and chief technology officer for TI.

TI will use the new design to stay competitive with other chip makers as device manufacturers demand chips that can support the convergence of communications and computing on mobile devices, and the growing use of portable multimedia, gaming and productivity applications.

Faster chips could feed more frames per second to a mobile phone video display, or allow wireless users to run simultaneous applications, such as playing a 3-D video game while holding a video conference with other players and sending e-mail in the background.

The design could also give TI a manufacturing advantage over competitors, since it doubles the number of chips produced on each 300-mm silicon wafer.

TI's claims of speed and efficiency are similar to an announcement made by Intel Corp. at the same conference, the Symposium on VLSI Technology, in Honolulu.

Intel announced plans to build chips by 2010 that use "tri-gate transistors" to better insulate electrical flow, enabling either a 45 percent increase in speed or a 35 percent reduction in total power used, compared to the company's current 65-nm process transistors.

The two designs also share a technical approach. Both achieve their technical gains by reducing electrical capacitance through a combination of "strained silicon" and low-k, or low-resistance, dielectric materials.

Both chips also use the CMOS (complementary metal oxide semiconductor) manufacturing infrastructure, but the hallmark of TI's system-on-chip design is its ability to integrate many features onto a single chip, from digital RF functionality to analog components such as resistors, inductors and capacitors.

TI's technique boosts transistor density by using immersion photo-lithography instead of dry lithography, allowing TI to shrink its 45-nm SRAM (static RAM) cell to just 0.24 square microns, up to 30 percent smaller than competitors' devices, the company said.

TI plans to build the new processors in its DMOS6 facility in Dallas, beginning production in mid-2008.

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