Intel's new emphasis on low power suits me to a T. The company's present take on low power is backed with some specious marketing that pretends the CPU is the only system component that draws current. Even so, Intel earns my nod for moving its Core microarchitecture, the son of a son of a Pentium III, to the top shelf. Core and the rest of Intel's road map are not, however, secret weapons that will slice AMD to little bits. AMD is not standing still.
There will always be a need for mainstream CPUs that meet the challenge of "damn the kilowatts, full speed ahead!" AMD's Opteron, Athlon FX, Turion, and Athlon X2 CPUs own the high-performance mantle; Intel will not recover it, and it knows that. Intel is playing on the fact that the coming round of high-performance server and desktop AMD64 processors, due midyear and dubbed Revision F, look like monsters compared with Intel's tiny Core. AMD64 Revision F uses a bigger die and therefore a bigger socket. Rev F CPUs will consume more power.
Increases in heat and size are unavoidable, given that AMD chose to put a lot more iron inside the chip. But AMD will put more innovation inside as well, innovation that serves customers now and signals where AMD is likely to go when it shifts to a 65-nanometer manufacturing process in 2007.
To refresh your memory, today's dual-core Opteron is an x86-compatible server CPU that comprises a pair of totally independent cores, each of which is identical to a discrete Opteron processor. Each Opteron core has its own Level 2 cache, an approach that differs from Intel's shared cache. But Intel's vaunted shared core advantages are offset by Opteron's Direct Connect architecture that runs dedicated HyperTransport bus links among all cores in a multiprocessor, multicore server, not just across cores within a single physical CPU. Opteron also incorporates on-chip memory and I/O controllers, the architectural features that leave Intel in the dust on performance no matter how fast Intel cranks its FSB (front-side bus) -- the link between CPUs and peripherals -- and memory hub. Opteron has neither an FSB nor a memory hub. These are not only factors in performance but also in total system power consumption -- the basis of an honest performance-per-watt analysis -- because Opteron systems are simpler in design and require fewer components than Intel's.
AMD is blending a couple of new ingredients into Revision F. The first is an upgrade to Opteron's on-chip memory controllers that makes the CPUs compatible with DDR2 memory. That boost will have more impact on Opteron performance than Intel's embrace of DDR2 had on its x86 designs, simply because there's no glue circuitry between Opteron CPUs and memory. Intel can implement whatever flavor of memory-to-CPU glue it likes, but as long as it's off-chip, much of the performance gain is lost to collisions among CPUs and with I/O traffic. In an Opteron server, there is one dedicated memory controller for each physical CPU.
AMD64 Revision F will also ring in hardware virtualization, formerly known as Pacifica but now bearing the more descriptive and virile moniker Secure Virtual Machine.
Next week, I'll lay out the details of SVM and discuss what Revision F and AMD's coming shift to a 65-nanometer process portend for the x86 race and for IT.