Toshiba has produced the first functional test chip which conforms to a new integrated-circuit architecture called X, which includes interconnects using diagonal pathways as well as the traditional grid-like vertical and horizontal pathways in use today.
The X architecture can provide improvements in chip performance over the traditional grid-like Manhattan design by enabling chip designs with less wiring and fewer connectors between wiring layers, or vias, the X Initiative consortium said Tuesday in a statement.
The technique is suitable for mass production of chips and the first production chips are expected in 2004, the consortium said.
The five metal-layer test chip was produced using a 90-nanometer process technology, currently the most advanced manufacturing process used to manufacture commercial chips today.
Compared to a chip of similar functionality using only Manhattan interconnects, the X Architecture implementation used 14 percent less total wire length for the interconnects between transistor gates and 27 percent fewer vias, according to the statement. Future developments should enable the wiring on a chip to be reduced by more than 20 percent and the number of vias to be reduced by more than 30 percent, it said.
The X Initiative is a consortium of over 20 companies involved in the semiconductor business, including Toshiba, Matsushita Electric Industrial Co., Ltd., STMicroelectronics, Cadence Design Systems, Inc., Nikon Corp. and Leica Microsystems AG.