AMD proposes speedier x86 instructions for multimedia

AMD. has proposed a new instruction set for its x86 microprocessors to render graphics faster. The SSE5 instructions will appear in chips in 2009.

Advanced Micro Devices wants developers to start thinking about how they can speed up their software using new instructions that will appear in the company's processors from 2009. The additions could simplify the way developers code the iterative calculations used to shade graphics, render photos or add spatial effects to audio.

Future x86 processors based on AMD's 64-bit Bulldozer core will understand the expanded instruction set, which the company calls SSE5. AMD published a note to developers about the SSE5 specification on Thursday.

Each of the new instructions will process several pieces of data with one instruction, a feature called Single Instruction, Multiple Data (SIMD). Intel added the first Streaming SIMD Extensions (SSE) instructions to the x86 instruction set in 1999, and has introduced several generations since. It published the programming reference for SSE4, the most recent, in April.

AMD has typically followed Intel's lead by incorporating support for that company's extensions in its processors. With SSE5, AMD hopes to give developers and software buyers an extra reason to choose its processors over those of Intel.

SSE5 defines 47 new basic instructions for speeding the execution of single-thread processes. One type, called multiply-add-accumulate, will allow developers to accumulate the results of many iterations of similar operations without a separate intermediate addition, speeding the kind of calculations used to render graphics or create 3D audio effects. Another allows them to multiply the contents of two registers, storing the result in a third -- a so-called three-operand instruction that can save developers juggling data between registers.

If software buyers are to benefit from the additional performance of these instructions, though, developers will need software tools such as compilers that optimize their code to use them. By publishing the specifications now, AMD is giving tool builders some of the information necessary to adapt their compilers before the first Bulldozer chips are released in 2009.

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Peter Sayer

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