Intel to detail roadmaps, improvements at MPF

Chip giant Intel Corp. will continue its trend of preaching about "more than gigahertz" at the Microprocessor Forum in San Jose, which begins Monday.

The show's opening keynote, given by Intel Fellow Justin Rattner, will focus on the future of computing systems. "It used to be speed first, everything else second; now designers are starting to prioritize different items together," Intel spokesman Seth Walker said Thursday.

Intel's vision of moving beyond gigahertz was introduced in August, when Paul Otellini, executive vice president and general manager of the Intel Architecture Group, said there were other ways to improve chip performance beyond simply increasing clock speed. Otellini made the remarks in his keynote at the Intel Developer Forum (IDF). Rattner will discuss "balancing and prioritizing power and performance, with a focus on power in particular," Walker said. Rattner will also discuss some of the new system and chip designs in the industry, including thread-level parallelism, the technology on which Intel's Hyper-Threading technology is based. Hyper-Threading, also introduced at IDF in August, is essentially the same technology as SMT (Simultaneous Multi-Threading), the technology Intel gained for its 64-bit Itanium processor when it agreed to purchase the intellectual property behind Compaq Computer Corp.'s Alpha family of RISC (reduced instruction set computing) processors. Hyper-Threading lets a single processor act as two processors and take two sets of instructions, ideally increasing performance.

Hyper-Threading is expected to first be released on Intel's Xeon chips for servers and workstations in the first half of next year, and Rattner is expected to give more details on those plans as well, Walker said. Rattner will also discuss how similar technologies can be carried over to desktop and mobile products, Walker said.

Later in the day on Monday, Bob Jackson, principal engineer with Intel's mobile platforms group, will give new details on Intel's upcoming mobile Pentium 4 processors, Walker said. "Those will include all the technologies of their (desktop) counterparts, but also some new power technology designed specifically for the mobile marketplace," Walker said.

Jackson will also give further technical disclosure on "Banias," another future mobile processor, which is expected in 2003. "He'll talk about the difference between Banias and what we have now," Walker said. One technology expected to be used in Banias will be "micro ops fusion," in which instructions are combined for faster execution.

On Tuesday, Dileep Bhandarkar, director of Intel enterprise architecture labs, will give an update on Intel's server and workstation roadmap. He will include the first details about Intel's multiprocessor Xeon server chip, which will use Hyper-Threading and is due in 2003, Walker said. The company will also discuss new benchmarks, showing that its next-generation 64-bit McKinley processor will demonstrate a greater increase in performance over its current 64-bit Itanium processor than Intel had expected, Walker said.

Finally, on Thursday, Intel Fellow Matt Adiletta will disclose plans for its future network processors, Walker said. "These will be the first technical details for the next-generation processors based on XScale microarchitecture," Walker said. XScale is Intel's next step in improving its StrongARM architecture, which powers various devices running Microsoft's PocketPC operating system. Intel has said its XScale chips will be designed to be used in everything from storage equipment to routers and cell phones.

The Microprocessor Forum, in San Jose, runs from Monday, Oct. 15, through Friday, Oct. 19. More information can be found on the Web at http://www.mdronline.com/mpf/index.html/.

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