Random chip structures to reduce manufacturing cost

  • Tom Krazit (IDG News Service)
  • 21 October, 2003 09:24

A new chip-making technique developed by researchers at three U.S. universities could help lower the cost of future chips by replacing transistors with wires made from gold atoms and organic molecules that connect randomly placed structures, the team announced Monday.

The team created working microelectronic systems called nanocells by submersing a silicon chip with disordered gold deposits into a solution of organic molecules and applying an electric current to the solution. This creates numerous nanowires between the gold deposits that can carry signals between the structures, said James Tour, an organic chemist with Rice University, based in Houston.

Most chips are built with millions of transistors that perform the essential logic tasks required to execute computer instructions. Chip designers must know exactly where to place each transistor on a chip, and program the function of that transistor prior to the manufacturing process, Tour said.

The precise placement and alignment of these transistors is an expensive and complicated process that requires billions of dollars for manufacturing equipment and facilities, Tour said. The team has developed a way to use these self-assembling structures to perform logic tasks without the need for as many transistors, which could eliminate a great deal of the complexity and cost from chip manufacturing, he said.

Most chip designers want to know exactly where every structure on a chip is placed, but as chip companies develop smaller and smaller transistors, it will become impractical to keep track of all those structures, Tour said. The team's technology can scale down to the extremely small sizes on the road maps of major chip manufacturers, he said.

The nanocells are allowed to randomly develop connections between structures and are then trained to act as logic or memory chips after they are assembled, Tour said. Chips for basic electronic devices might only need a few hours of programming, while chips for supercomputers might require a couple of weeks to set in order, he said.

Much like neural pathways in the brain, the nanowires are trained to handle certain tasks through repetition, Tour said. The chip's complexity is created by this postmanufacture process, rather than by the costly process of assigning each transistor a task before the chip is built, he said.

The team's prototype nanocell was used to make a nonvolatile memory chip, which can store information for an extended period of time without an electronic refresh, unlike RAM chips found in PCs, which need to be refreshed thousands of times a second. Examples of nonvolatile memory include flash memory chips used in cell phones and personal digital assistants.

Researchers were able to develop nanocells that held their memory state for about nine days at room temperature, Tour said.

The researchers have also shown how to use the nanocell as a logic gate. Transistor gates on current processors are very small, but the use of molecular components could shrink gate sizes beyond what CMOS (contemporary metal-oxide semiconductor) manufacturing techniques are thought to be capable of developing.

This technique wouldn't replace transistors entirely, but would rather supplement them, Tour said. For instance, the work previously done by five transistors could be done by a series of these nanowires, with a single transistor used to amplify that output, he said.

Products made with this technology are at least a decade away, Tour said.

The research will appear in the Oct. 29 issue of the Journal of American Chemical Society, and was sponsored by the Defense Advanced Research Projects Agency (DARPA), the U.S. Office of Naval Research and Molecular Electronics Researchers from Rice, Pennsylvania State University and North Carolina State University participated in the project.